Picking Decoupling Capacitors: SRF, ESL & Math

Why Decoupling Isn't as Simple as "Slap a 100 nF on It"

Every engineer has heard the rule of thumb: stick a 100 nF capacitor next to every IC power pin and call it a day. And honestly? It works fine for a lot of circuits. Until it doesn't.

The moment your FPGA starts pulling 20 A transient currents at 500 MHz, or you're chasing down a spurious tone in your ADC that keeps pointing back to supply noise at 800 MHz, that lonely 100 nF cap suddenly looks pretty inadequate. Understanding why this happens means getting familiar with three parasitic parameters that most datasheets mention once, in tiny print, buried somewhere after page 47: ESR, ESL, and the self-resonant frequency they conspire to create.

Most engineers skip the math here and regret it later when they're debugging a board at 2 AM.

The Real Model of a Capacitor

Here's the thing about physical capacitors — they're not pure capacitances. Never have been. What you actually get when you solder down that little ceramic rectangle is a series RLC circuit. The impedance looks like this:

where $C$ is the nominal capacitance (the number on the label), $L$ is the equivalent series inductance or ESL, and $R$ is the equivalent series resistance, the ESR. At low frequencies, the capacitive reactance $X_C = 1/(2\pi f C)$ dominates and everything behaves like you'd expect from your textbook. But crank up the frequency and the inductive reactance $X_L = 2\pi f L$ starts taking over.

Right in the middle of this transition, something interesting happens: the capacitive and inductive reactances cancel each other out perfectly. You're left with just the ESR — the absolute lowest impedance that capacitor will ever present to your circuit. That crossover point is called the self-resonant frequency, or SRF:

Below the SRF, your part acts like a capacitor. Above it? It's an inductor. This is the single most important concept in decoupling design, and it's the reason you can't just throw capacitors at a problem and expect them to work at every frequency. A capacitor only decouples effectively in a band centered around its SRF. Outside that band, you're fighting physics.

Key Parameters and What They Mean for Your PDN

Your power distribution network — the PDN — has a target impedance it needs to maintain. You can usually derive this from the allowed supply ripple and the worst-case transient current:

Let's say you're working with a 1.0 V rail feeding an FPGA that can pull 5 A transients, and you've budgeted 3% ripple. Your target impedance works out to $Z_{\text{target}} = 1.0 \times 0.03 / 5 = 6\,\text{m}\Omega$. That's 6 milliohms. That's a brutally low number, and you have to maintain it across the entire bandwidth where your IC is pulling current. Good luck.

This is where ESR and ESL stop being abstract datasheet parameters and start mattering a lot:

• ESR sets the impedance floor at resonance. Take a typical 100 nF 0402 MLCC — it might have an ESR somewhere between 10 and 50 mΩ. If your target impedance is 6 mΩ, a single cap physically cannot meet that spec. The laws of physics won't allow it.

• ESL determines how fast the impedance climbs above the SRF. A 0402 package typically carries about 0.5 nH of ESL. Drop down to an 0201 and you might get 0.3 nH. Lower ESL pushes your effective bypass range higher in frequency, which is exactly what you want when you're dealing with fast digital logic.

The parasitic inductance isn't just an academic concern — it's the reason your decoupling stops working at high frequencies.

Worked Example: Bypassing a 1.0 V FPGA Rail

Let's walk through an actual design scenario. We need to keep $Z_{\text{PDN}} < 6\,\text{m}\Omega$ all the way up to 500 MHz. This is a real requirement you'd see on a modern FPGA design.

Step 1: Choose a capacitor. We'll start with a 100 nF 0402 X7R MLCC. From the datasheet, we find ESR = 20 mΩ and ESL = 0.5 nH. Pretty typical values for this package size. Step 2: Calculate the SRF. Plug the numbers into the formula:

Work through the arithmetic and you get $f_{\text{SRF}} \approx 22.5\,\text{MHz}$. At this frequency, the impedance equals the ESR: 20 mΩ. That's actually not bad — it's only about 3× our target. But we're not operating at 22.5 MHz.

Step 3: Check impedance at 500 MHz. This is way above the SRF, so the impedance is almost entirely determined by the ESL:

That's 1.57 ohms. Our target was 6 milliohms. We're off by a factor of 260. At 500 MHz, this 100 nF capacitor is essentially invisible to the circuit. It might as well not be there.

Step 4: Add a higher-frequency cap. We need something with a higher SRF. Let's try a 1 nF 0201 cap with ESR = 50 mΩ and ESL = 0.3 nH:

Much better — we're in the right frequency neighborhood now. At 500 MHz its impedance is roughly $2\pi \times 500 \times 10^6 \times 0.3 \times 10^{-9} \approx 0.94\,\Omega$. Still too high for a single cap, but we're getting closer to reality.

Step 5: Use parallel capacitors. Here's the good news: when you place $N$ identical capacitors in parallel, the impedance divides by $N$. To hit our 6 mΩ target at the SRF of the 100 nF cap (where $Z = 20\,\text{m}\Omega$), we need:

Four 100 nF caps in parallel gets us to our target impedance at 22.5 MHz. But for the 500 MHz range, we need a completely separate bank of those 1 nF caps — or maybe even smaller values — each targeting a different frequency band. This is exactly why real PDN designs use multiple capacitor values. Each value covers a different frequency decade. You're building a distributed filter network, not just slapping down random caps.

The Effective Bypass Range

There's a useful concept here called the effective bypass range — the frequency span over which a capacitor actually keeps impedance below your target. You can estimate the upper bound by finding where the inductive reactance equals your target impedance:

For our 100 nF cap with 0.5 nH ESL and a 20 mΩ target (single cap): $f_{\text{upper}} = 0.02 / (2\pi \times 5 \times 10^{-10}) \approx 6.4\,\text{MHz}$. That's the frequency where, above the SRF, the cap stops being useful on its own. Below the SRF there's a symmetric lower bound where the capacitive reactance becomes too high. The calculator handles both limits automatically so you don't have to work through this every time.

The practical takeaway? Each capacitor has a finite bandwidth where it's actually doing its job. Outside that window, you need different capacitors.

Common Pitfalls

A few things will bite you if you're not careful:

Ignoring ESL from PCB vias and traces. That 0.5 nH ESL figure in the datasheet? That's just the package itself. The moment you add a via to route down to an internal power plane, you're adding another 0.5 to 1.0 nH of inductance. Sometimes more. Your actual SRF just got cut significantly. The fix is to keep decoupling caps on the same layer as the IC whenever possible, or use very short, wide connections to minimize via inductance. Anti-resonance between parallel caps. When you put two different-value caps in parallel, they can create a high-impedance peak between their respective SRFs. The impedances don't just add nicely — they interact. You can end up with a resonant spike that's actually worse than having no cap at all in that frequency range. Simulation or very careful value spacing is essential. This is one of those things that looks fine on paper and then ruins your day during testing. Assuming ceramic caps hold their rated value. Here's a fun surprise: that 100 nF X7R cap in an 0402 package? Under 1.0 V DC bias, it might actually be delivering 60 to 70 nF of capacitance. Sometimes worse. The ferroelectric material in ceramic caps loses capacitance under DC bias, and smaller packages lose more than larger ones. Always check the manufacturer's DC bias curves. Your SRF calculation is only as good as your actual capacitance value.

Try It

Plug your capacitor values, ESR, ESL, and target impedance into the calculator and you'll instantly see the SRF, the impedance at your frequency of interest, the effective bypass range, and how many caps you actually need in parallel. Open the Decoupling Capacitor Selection Calculator and take the guesswork out of your next PDN design. It beats doing all this math by hand at midnight before a board spin deadline.