How Much Current Can a Microvia Carry?

A very small annulus

A microvia is laser-drilled and blind, connecting two adjacent layers. IPC-2226 defines it by geometry: 0.15 mm diameter or less, with a depth-to-diameter ratio of 1:1 or better.

Like any plated via, its copper is a thin-wall annulus, not a plug:

A 100 µm microvia with 18 µm plating gives 0.00464 mm² — about a fifth of a 0.3 mm through-hole via.

That is why the current question comes up at all. And it has a genuinely surprising answer.

It has less resistance than a through-hole via

Resistance is $\rho L / A$, and the length term wins decisively.

• 100 µm microvia, 75 µm deep: 0.284 mΩ
• 0.3 mm through-hole via, 1.6 mm board: 1.30 mΩ

A fifth of the copper area, but only about 5 % of the length, so it ends up more than four times lower in resistance. Microvias are excellent for power delivery in HDI stack-ups, and the intuition that a smaller via must be worse is simply wrong for DC.

Two answers for current capacity

IPC-2221 gives conductor current capacity as:

with $A$ in square mils. The exponents come from a fit to measured trace data. The constant $k$ encodes how easily heat escapes: 0.024 for internal conductors buried in laminate, 0.048 for external conductors on an outer surface — a factor-of-two derating for being buried.

Which one applies to a microvia is genuinely ambiguous.

It is buried, arguing for 0.024. But it is also only 50–100 µm long and bonded at both ends to copper pads that conduct heat far better than laminate does, arguing for 0.048.

For the 100 µm microvia at 10 °C rise:

• Internal class: 0.276 A
• External class: 0.552 A

Most HDI design rules budget 0.5 to 1 A per microvia, which sits at or slightly above the upper bound. That is not unreasonable given the pad heatsinking, but it is worth knowing you are near the optimistic end of the model rather than comfortably inside the conservative one.

The barrel is not what fails

Here is the part that reframes the whole question.

Model the barrel as a conduction path: $\theta = L/(k_{Cu} A)$ gives about 42 °C/W. At 0.25 A the dissipation is 0.018 mW, so the steady-state rise is 0.0007 °C.

Seven ten-thousandths of a degree. The IPC-2221 capacity figure and the actual barrel temperature rise are describing entirely different things, and they disagree by orders of magnitude.

What actually fails is the target-pad interface. Under thermal cycling the z-axis expansion of the dielectric pulls the plated barrel away from the pad it lands on. Microvia reliability is qualified by thermal shock testing per IPC-TM-650 2.6.27, not by a current formula.

So treat the IPC-2221 number as a plating and electromigration guardrail, not a temperature prediction. The mechanism it was fitted to — a long conductor shedding heat along its length — is not the mechanism operating here.

Geometry constraints that actually bind

Aspect ratio. IPC-2226 caps depth-to-diameter at 1:1 and most fabricators prefer 0.75:1. Beyond that the laser-drilled hole tapers too sharply for the plating chemistry to reach the target pad with uniform thickness, and the thin plating at the base becomes the failure point. This constraint bites long before current does. Plating minimum. IPC-6012 Class 2 permits 18 µm minimum against a 20 µm average. Capacity scales as area to the power 0.725, so design against the minimum. Current density. Above roughly 100 A/mm², electromigration and plating voids become a concern that no temperature-rise calculation reveals. A single 100 µm microvia hits that at about 0.46 A.

Stacked versus staggered

Stacked microvias give a shorter, lower-resistance path and save routing area. They are also the most common HDI failure mode under thermal cycling, because the stacked interfaces accumulate stress.

Stagger them where the layout allows, with a solid pad between layers. IPC-6012 Class 3/A adds specific requirements for stacked structures precisely because they are the weak point.

If you must stack for routing density, that is a reliability decision, not a routing decision, and it should be made with whoever owns the qualification plan.

Sizing a rail

For 2 A using the conservative 0.276 A per via: eight vias minimum, ten with margin for plating variation and uneven current sharing. Current does not distribute evenly across a cluster — the via nearest the incoming current takes more than its share.

A tight cluster under the pad is standard practice, and it gets you the resistance benefit as well: ten microvias in parallel is 0.028 mΩ, which is effectively a short.

The microvia current capacity calculator reports both IPC classes, barrel area, resistance for single vias and arrays, current density, self-heating, and IPC-2226 aspect-ratio checks.