Via Resistance Is Not Zero: Sizing Vias for Power Rails

The cross-section is an annulus

Drill a 0.3 mm hole and plate its wall with 25 µm of copper. The copper does not fill the hole — it lines it. The conducting cross-section is a thin-wall annulus:

For that via: 0.0216 mm². If you had assumed a solid 0.3 mm copper plug you would have calculated 0.0707 mm² — over three times too much, and a current capacity estimate that is wrong in the dangerous direction.

Through a 1.6 mm board at 25 °C that annulus gives 1.30 mΩ.

Where that matters

At 1 A, 1.30 mΩ produces 1.30 mV of drop and 1.30 mW of dissipation. Nobody cares.

At 20 A through a single via: 26 mV and 521 mW. Now you care about both. Half a watt in a structure a third of a millimetre across, with only the laminate and the connecting copper to carry the heat away, is a hot spot you will find with a thermal camera.

The modelled temperature rise for the 1 A case is a quarter of a degree, against a via thermal resistance of about 192 °C/W. That thermal resistance is the number that scales badly — it is fixed by geometry, so dissipation rising as $I^2$ walks the rise up quickly.

Parallel vias divide, and that is the whole technique

Resistance divides by $N$. Eight 0.3 mm vias in parallel through a 1.6 mm board give 0.163 mΩ — comparable to a few millimetres of wide trace, and negligible against almost any rail budget.

The practical rule most power designers use is roughly one standard via per amp of continuous current, which keeps temperature rise under a few degrees and leaves margin for the fact that current does not share evenly. It does not: the via nearest the incoming current sees more than its share, and a cluster of eight does not behave like eight identical resistors in parallel. Adding 20 to 30 % more vias than the arithmetic demands is cheap insurance.

Temperature makes it worse, and it compounds

Copper resistivity rises 0.393 % per °C. At 85 °C a via has 26 % more resistance than at 20 °C.

That is a positive feedback path: current heats the via, the hotter via has more resistance, more resistance dissipates more power. It is bounded by conduction into the surrounding copper, but it means the worst-case calculation has to be run at the worst-case ambient plus the self-heating, not at 25 °C.

For a power path in an enclosure that runs at 70 °C internally, computing via resistance at room temperature understates it by around 20 %.

What actually helps

More vias beats bigger vias, but bigger vias beat thicker plating. Area scales as $t(D - t)$, so at 25 µm plating the diameter term dominates: going from 0.3 mm to 0.4 mm gains 36 % more copper, while going from 25 µm to 35 µm plating gains 35 % — comparable, but plating thickness is a fab-wide process parameter you do not control per-net, while drill size is yours. Design to minimum plating, not nominal. IPC-6012 Class 2 specifies 20 µm average with 18 µm minimum. Worst-case resistance uses the minimum. Place vias inside the pad or immediately adjacent. The trace between the pad and a distant via stitch is usually higher resistance than the vias themselves — a 10 mm run of 0.25 mm trace in 1 oz copper is about 20 mΩ, fifteen times the via. Copper-filled vias for the extreme cases. Filling converts the annulus into a solid cross-section, which is a large gain, but it is a significant cost adder. It earns its place above roughly 10 A per via, and rarely below.

The frequency caveat

Everything above is DC. For power integrity at MHz, via inductance matters more than via resistance. A via is around 0.5 to 1 nH; at 100 MHz, 1 nH is 628 mΩ of reactance against 1.3 mΩ of DC resistance.

Parallel vias help both, which is convenient. But if the problem is a PDN impedance target across a wide band rather than a DC drop, size the via count against the inductance, and the DC resistance will look after itself.

The via voltage drop calculator works the annular cross-section, temperature-compensated resistance, drop, dissipation, and estimated rise for single vias and parallel arrays.