FDTD Simulation: Why 10 Gbps Signals Hate Via Stubs

The Via Is Not Just a Hole

At 100 MHz, a 0.3 mm drill via on a 1.5 mm FR-4 board is basically invisible from an electrical standpoint. You'll measure a fraction of an ohm of resistance and maybe 0.5 nH of inductance. Plug those numbers into your SPICE model and move on with your day. But try running a 10 Gbps SerDES lane through that same via on a 12-layer backplane and suddenly everything changes. The unused lower portion of the via barrel — what we call the stub — starts acting like a shorted transmission line stub. When it hits its quarter-wave resonance, you get a deep notch that can land right in the middle of your signal band. Not great.

This is where FDTD (Finite-Difference Time-Domain) simulation becomes incredibly useful. Unlike simple lumped-element models, FDTD actually solves Maxwell's equations on a 3D grid, so it captures the full electromagnetic behavior of the via transition. That means the impedance discontinuity at the pad, the barrel inductance, the stub resonance, and the capacitive loading from the anti-pad — all of it. The FDTD S-Parameter Simulator tool lets you run this kind of analysis right in your browser in seconds, without needing a full 3D EM solver license that costs more than a used car.

Setting Up the Simulation

Let me walk through the exact parameters for modeling a through-via on a standard 1.5 mm FR-4 PCB carrying a 10 Gbps signal. These are real-world numbers you'd actually use:

A few notes on why these specific values matter. The 3.0 mm trace width gives you 50 Ω on 1.5 mm FR-4 with 1oz copper — you can verify this with any microstrip impedance calculator. The via aspect ratio of 5:1 (1.5 mm depth, 0.3 mm drill) is pretty moderate. Most PCB manufacturers are comfortable going to 8:1 with standard drill bits and can push to 12:1 with laser-assist if you really need it.

The center frequency of 2.4 GHz with a 4 GHz span covers DC to 4.4 GHz, which is important because it captures both the Nyquist frequency of a 10 Gbps NRZ signal (5 GHz) and the first stub resonance. For this particular geometry, that resonance lands around 3.8 GHz. If you don't sweep wide enough, you'll miss the problem entirely — and that's how signal integrity issues make it to production.

What the FDTD Engine Is Actually Doing

When you click Run, the simulator discretizes your via geometry onto what's called a Yee grid. This is a staggered 3D mesh where electric and magnetic field components are offset by half a cell in both space and time. It's an elegant numerical trick that keeps the simulation stable and accurate.

The engine injects a Gaussian pulse at Port 1 (the microstrip feed end), then records the time-domain fields at Port 1 (reflected energy) and Port 2 (transmitted energy) until everything decays to near zero. The S-parameters you care about come from taking the Fourier transforms and computing the ratios:

The Normal mesh density uses roughly 10 cells per wavelength at the center frequency. That's adequate for a first-pass assessment and runs pretty quickly. Fine mesh will increase the cell count by 8× and take proportionally longer to solve, but you'll need it when the via barrel diameter is less than 3× the mesh cell size. Otherwise you're essentially trying to model a cylinder with too few voxels, and the results get sketchy.

Interpreting the S11 and S21 Results

For a through-via with no back-drilling on 1.5 mm FR-4, here's what you'll typically see in the output plots:

S21 (insertion loss): Pretty flat and near 0 dB from DC up to roughly 2 GHz, then you'll see a progressive rolloff. The real problem shows up as a sharp notch at approximately 3.8 GHz, dropping to somewhere between −15 and −20 dB. That's your stub resonance screaming at you. S11 (return loss): Starts below −20 dB at low frequency, which is good. But then it rises to −10 to −15 dB near the stub resonance frequency as energy reflects back from the impedance mismatch. Interestingly, it often improves again at higher frequencies as the via impedance coincidentally re-matches — though by then your signal has already been destroyed by the notch.

The stub resonance frequency is the critical number you need to extract from this simulation. For a through-via where the signal enters at the top layer and exits at layer 3 (say, on a 10-layer board), the stub is everything below layer 3 — the unused portion of the barrel. Its resonant frequency follows this relationship:

where $v_p = c / \sqrt{\varepsilon_r}$ is the propagation velocity in the dielectric and $L_{stub}$ is the physical stub length. For FR-4 with εr = 4.4, you get $v_p = 3 \times 10^8 / \sqrt{4.4} \approx 1.43 \times 10^8$ m/s.

Let's work through some real examples. A 1.0 mm stub resonates at 35.7 GHz — completely harmless for 10 Gbps signals. A full 1.5 mm stub (signal exits at layer 1, nothing back-drilled) resonates at 23.8 GHz. That's still technically above the 5 GHz Nyquist frequency, but only by a factor of 4.7. That's cutting it close. Run the simulation with a 10 GHz span and you'll see the notch start creeping in by 8 GHz. Most engineers skip this validation step and regret it later when they're debugging why their eye diagram looks terrible.

Effect of Via Drill Diameter

Here's a useful experiment: change the Via Diameter parameter from 0.3 mm to 0.5 mm and re-run the simulation. You should observe several things happening:

• The stub resonance frequency shifts slightly lower. A larger barrel has more capacitance, which pulls the resonant frequency down.
• S21 insertion loss at low frequency gets a bit worse due to increased pad capacitance loading the trace.
• S11 at DC-to-1 GHz degrades by 2–4 dB as the larger anti-pad capacitance creates a bigger impedance mismatch with the trace.

This confirms an important SI rule of thumb: minimize via drill diameter for high-speed signals. It's not just about hitting aspect ratio targets for manufacturing — it's about reducing the via capacitance that lowers the local impedance. For a 0.3 mm drill on 1.5 mm FR-4, the via impedance is roughly 35–40 Ω. That's already 10–15 Ω below your 50 Ω system impedance, creating a discontinuity at every via transition. Some designs try to compensate by reducing the anti-pad diameter to shrink the capacitance, though you have to be careful not to violate your fab house's clearance rules.

When to Back-Drill

Back-drilling removes the stub by counter-boring from the opposite side of the board after plating. You're left with only a short stub remnant, typically 0.1–0.2 mm of drill-to-layer clearance. It adds cost — expect somewhere between $150 and $300 per panel depending on your fab house and panel size — but the improvement is dramatic. The notch literally disappears from your signal band entirely.

The rule of thumb is straightforward: if the stub resonance from the Via Stub Resonance calculator lands within 2× the signal Nyquist frequency, you need to back-drill. For 10 Gbps NRZ with a 5 GHz Nyquist frequency, that means back-drilling any stub that resonates below 10 GHz. For 25 Gbps PAM4, that threshold jumps to 25 GHz — which means back-drilling becomes nearly mandatory on backplane designs. There's just no way around it.

I've seen plenty of designs where someone tried to save a few hundred dollars per panel by skipping back-drilling, only to discover in testing that their signal integrity was completely shot. Then they're looking at a full board respin, which costs orders of magnitude more than just doing the back-drilling correctly the first time.

What to Do with the Results

Once the simulation confirms you have a stub resonance problem — and let's be honest, you probably do if you're running multi-gigabit signals through a thick backplane — here are your options in order of increasing cost:

1. Re-route to a shallower layer transition. If the signal can exit at layer 2 instead of layer 6, the stub becomes much shorter and the resonance moves way up in frequency. This is free if you catch it early enough in layout, but might require ripping up significant routing if you're deep into the design.

1. Reduce drill diameter. A smaller via gives you lower capacitance and pushes the resonance frequency slightly higher. The improvement is modest but sometimes it's enough to move the notch just outside your signal band. Check with your fab house about their minimum reliable drill size — pushing too small increases manufacturing yield risk.

1. Add a via-in-pad with back-drill. This gives you the best SI result but carries the highest cost. Via-in-pad also helps with thermal performance on power components, so sometimes you can justify it on multiple fronts.

1. Use blind or buried vias. These eliminate the stub entirely by only drilling as deep as needed. The signal integrity is excellent, but the fabrication complexity increases significantly. You're looking at a much more expensive board and potentially longer lead times.

Run the FDTD simulation at each stage to confirm the resonance has actually moved out of band before you send the design to fab. An hour of simulation time now is infinitely cheaper than discovering the problem after you've built 500 boards. Trust me on this one.

Use the FDTD S-Parameter Simulator to model your via geometry directly in the browser and see exactly where your stub resonance lands.