A Via Is Not a Capacitor: Excess Reactance and Rise Time
Via capacitance sounds alarming until you subtract what a matched line would have had anyway. Only the excess is a discontinuity — and shrinking capacitance past the optimum makes reflection worse, not better.
Contents
The number that scares people
A 1.6 mm through via with a 0.3 mm drill, 0.6 mm pad and 1.0 mm antipad on FR-4 has about 0.57 pF of pad-to-antipad capacitance and 1.14 nH of barrel inductance.
0.57 pF sounds like a lot to hang off a fast signal. It is not, and the reason is the part most via discussions skip.
Subtract what a line would have had
An ordinary section of transmission line also has inductance and capacitance. That is what makes it a transmission line. A properly terminated line does not reflect, despite having plenty of both.
What a receiver sees is the imbalance. So subtract what a matched section of the same electrical length would have contributed:
For the via above in a 50 Ω line:
- L/Z₀² = 0.456 pF
- C_exc = 0.572 − 0.456 = 0.116 pF
So four fifths of that alarming 0.57 pF is not a discontinuity at all. Only 0.116 pF is.
Exactly one of C_exc and L_exc is positive, and which one tells you the character of the via. Here C_exc is positive, so the via is capacitive — the usual case for a large pad in a tight antipad.
The clean statement of this: a via whose √(L/C) equals Z₀ is electrically invisible, no matter how large and are individually. This one is √(L/C) = 44.6 Ω against a 50 Ω line, which is why it is close to invisible but not quite.
Turning excess into timing
A small shunt capacitance is charged through the source impedance in parallel with the load — . That gives a first-order time constant τ = Z₀·C_exc/2, and converting to a 10–90 % edge multiplies by :
Edges combine in quadrature, so:
On a 400 ps LVDS edge that is ps. A 0.013 % effect. On a 20 ps edge the same 6.38 ps gives 21.0 ps — a 5 % effect.
Quadrature addition is why via design is forgiving at moderate edge rates and unforgiving at fast ones. The geometry did not change; the spectrum did.
Reflection scales worse than timing
Peak reflection from a small discontinuity is:
Inversely proportional to rise time — not in quadrature. So it grows in direct proportion to edge rate:
- 2 ns edge: 0.145 %
- 400 ps edge: 0.73 %
- 100 ps edge: 2.9 %
- 30 ps edge: 9.7 %
Twenty times faster edge, twenty times the reflection. This is the term that actually kills fast links, and it is the reason a via that was fine on the previous generation of a product becomes a problem when the SerDes rate doubles.
Do not maximise the antipad
Here is the counterintuitive part, and it is the most useful thing in this article.
The instinct is that less capacitance is always better, so open the antipad as far as the plane allows. Try it on the via above — grow the antipad from 1.0 mm to 2.0 mm:
- Capacitance drops from 0.572 pF to 0.163 pF
- Reflection at a 100 ps edge rises from 2.9 % to 7.3 %
The via went too far. With so little capacitance, L_exc = L − C·Z₀² turned positive and the via is now inductive-dominant. It is just as much a discontinuity as before — in the other direction.
The target is not C = 0. It is C = L/Z₀². Watch the excess capacitance output cross zero and stop there.
Self-resonance sets the model's validity
L and C resonate at f₀ = 1/(2π√(LC)) — 6.24 GHz for this via. The signal's knee frequency is 0.5/t_r: 1.25 GHz at 400 ps, 5 GHz at 100 ps.
Once the knee gets within about a third of f₀, the via is no longer electrically short and the lumped model becomes optimistic. Past that, only a 3D field solver gives a trustworthy answer. The same applies once the computed reflection exceeds roughly 30 % — the small-discontinuity approximation the reflection formula rests on has broken down.
Note this is a different mechanism from via stub resonance. The λ/4 stub resonance comes from an unused length of barrel acting as an open transmission line and produces a deep narrow insertion-loss null. It is usually the lower frequency of the two and the more damaging. Both need to stay above your knee.
What actually helps
Remove non-functional pads on layers the via does not connect to. Usually the single largest capacitance reduction available, and it costs nothing. Back-drill the stub. Shortening the barrel reduces and together, pushing self-resonance up rather than trading one parasitic for the other. It also kills the λ/4 stub resonance, which is often the bigger win. Tune the antipad toward C = L/Z₀², not toward maximum. Use the correct barrel length. After back-drilling, the signal only traverses the remaining length. Using full board thickness overstates both parasitics substantially. For differential pairs, model each via at the single-ended impedance. A 100 Ω pair is two 50 Ω lines.The via step response calculator reports L, C, both excess terms, via impedance, self-resonance, edge degradation, and peak reflection for a given rise time.
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