Predicting Radiated Emissions Before You Fail the Test

Why Bother Estimating Before the Chamber?

EMC testing is expensive. A single day in a fully compliant anechoic chamber runs $2,000–4,000 depending on where you are, and that's before you factor in engineering time, travel, and the inevitable "we need to come back next week" when something fails. Most engineers treat radiated emissions as a black box until they're staring at a failing plot, but it doesn't have to be that way.

The physics of radiated emissions from PCB current loops is well understood. If you know the loop current, the loop area, and the frequency, you can estimate the electric field at a given distance with reasonable accuracy. "Reasonable" here means within 6–10 dB of reality for simple geometries — not perfect, but enough to tell you whether you're going to pass comfortably, fail spectacularly, or land in the uncomfortable gray zone where layout tweaks might save you.

The Underlying Model

A small current loop acts as a magnetic dipole. At distances much greater than a wavelength, the radiated electric field from such a loop is:

where $E$ is the electric field in µV/m, $I$ is the peak loop current in amps, $A$ is the loop area in m², $f$ is the frequency in MHz, and $r$ is the measurement distance in meters. This formula assumes far-field conditions and a loop that's electrically small compared to the wavelength.

The $f^2$ term is the killer. Double your frequency, quadruple your emissions. This is why high-speed digital designs with fast edges — lots of harmonic content — tend to fail at frequencies way above the fundamental clock rate.

CISPR 22 Class B (now CISPR 32, but everyone still calls it Class B) specifies limits at 10 meters. At 30 MHz the limit is 30 dBµV/m; it rises to 37 dBµV/m above 230 MHz and stays there through 1 GHz. These aren't arbitrary numbers — they're what regulatory bodies decided was acceptable for residential environments. Miss them by 3 dB and you're probably fine after some filtering. Miss them by 15 dB and you're redesigning the board.

A Worked Example: 100 MHz Clock Distribution

Let's say you've got a 100 MHz clock routed on an inner layer of a 4-layer board. The signal runs 25 mm (0.025 m) before reaching a buffer IC, and the return path is on an adjacent ground plane. With a 0.2 mm dielectric thickness, the loop area is roughly:

That's 5 mm² — pretty small, which is good. Now suppose the clock signal swings 3.3V into a 50 Ω load, giving a peak current of 66 mA (0.066 A). At the third harmonic (300 MHz, where CISPR limits get tighter), the estimated field at 10 m is:

Converting to dBµV/m: $20 \\log_{10}(0.391) = -8.2$ dBµV/m.

The CISPR 22 Class B limit at 300 MHz is 37 dBµV/m. Your margin is a comfortable 45 dB. You're fine — at least from this particular loop.

But here's where it gets interesting. What if the return path isn't directly under the trace? Suppose there's a split in the ground plane and the return current has to detour around it, creating a loop area of 200 mm² instead of 5 mm². That's 40× larger.

Still passing, but your margin just dropped to 13 dB. Add a few more loops like this, account for cable radiation, and suddenly you're sweating.

Open the Radiated Emission Estimate calculator to run your own numbers.

When This Model Works (and When It Doesn't)

The small-loop approximation works well when the loop perimeter is less than about λ/10. At 300 MHz, that's 10 cm — most PCB structures qualify. It also assumes you're measuring in the far field, which at 300 MHz starts around 1.5 meters. The 10-meter CISPR distance is solidly in far-field territory.

The model breaks down for distributed structures like long cables, slot antennas (gaps in ground planes), and anything where the current distribution isn't uniform. It also ignores reflections from the chamber floor and nearby metal — the real test environment is messier than free space.

Don't expect this estimate to match your chamber results exactly. Expect it to get you in the right ballpark. If the calculator says you have 3 dB of margin, treat that as "probably failing." If it says you have 25 dB of margin, you can relax a bit.

Common Mistakes and Gotchas

Forgetting About Harmonics

A 50 MHz clock doesn't just radiate at 50 MHz. If it has fast edges — and most CMOS clocks do, with rise times under 1 ns — it has significant harmonic content out to 300 MHz and beyond. The third, fifth, and seventh harmonics often cause more trouble than the fundamental because of that $f^2$ term. Always check the harmonics, not just the clock frequency.

Underestimating Loop Area

Engineers routinely assume the return current flows directly under the signal trace. It usually does, if you've got a continuous reference plane. But vias that switch reference layers, splits in planes, and connectors with inadequate ground pins all force the return current to take longer paths. The actual loop area can be 10× or 100× what you'd naively calculate.

Using RMS Current Instead of Peak

The formula wants peak current, not RMS. For a sinusoidal signal, peak is √2 times RMS. For a square wave, peak equals the amplitude. Getting this wrong gives you a 3 dB error — not catastrophic, but it adds up.

Ignoring Cable Radiation

Your PCB might be clean, but the cables attached to it often aren't. A 1-meter USB cable with even a few milliamps of common-mode current is a far more efficient antenna than any trace on your board. This calculator focuses on loop radiation, which is useful for PCB design decisions, but don't forget that cables frequently dominate in the final test.

Assuming 10-Meter Results Scale Simply to 3-Meter

Some test houses use 3-meter distances for pre-compliance. The field scales as 1/r in the far field, so 3-meter results are about 10 dB higher than 10-meter results. But CISPR limits are specified at 10 meters, and the correlation factor isn't exactly 10 dB due to near-field effects at lower frequencies. Be careful when comparing.

Practical Design Implications

Once you've run a few estimates, patterns emerge. Reducing loop area is almost always the most effective fix — it's a linear relationship, so cutting area in half cuts emissions in half. Reducing current helps too, but you often can't change that without affecting circuit function.

Slowing down edges reduces harmonic content, which helps at high frequencies. A 10 ns rise time instead of 1 ns dramatically cuts the energy above 100 MHz. Series resistors on clock lines, ferrite beads, or simply choosing slower logic families all work.

Shielding and filtering are last resorts. They work, but they cost money and board space. It's almost always cheaper to fix the problem at the source.

Margin Philosophy

How much margin do you need? The honest answer is "more than you think." Real products have multiple emission sources that add (sometimes coherently), measurement uncertainty of ±3 dB, and production variation. A design that passes with 2 dB of margin in the lab will have units that fail in production.

I generally aim for 6 dB minimum margin on any individual source, and 10 dB if possible. If the calculator shows you're right at the limit, that's not "passing" — that's "probably failing after you add the power supply, the display, and the Bluetooth module."

Try It

Grab your schematic, identify your highest-frequency switching signals, estimate the loop areas, and open the Radiated Emission Estimate calculator. Run the numbers for the fundamental and at least the third and fifth harmonics. If you're within 10 dB of the limit on any of them, that's your signal to look harder at the layout before you spend money on chamber time.

It takes five minutes and might save you a week of debugging.