SMPS Control Loop Stability Analyzer
Model switch-mode power supply control loops using small-signal transfer functions. Get Bode plots of T(s), extract phase margin, gain margin, and crossover frequency, then run Monte Carlo trials over component tolerances (L ±20%, C ±20%, ESR ±50%, load ±30%) to compute manufacturing yield.
How It Works
Small-signal analysis models the SMPS as a linear time-invariant system around its operating point. The open-loop gain T(s) = Gc(s) × Fm × Gvd(s) × H(s) determines stability: Gc is the compensator, Fm the PWM modulator gain, Gvd the power stage plant (duty cycle to output voltage), and H the feedback divider.
Plant models: In voltage mode, Gvd(s) is the state-space-averaged model of the power stage, including the output capacitor's ESR and the load. The buck plant has two LC poles and one ESR zero — second-order with 180° phase lag. Boost and buck-boost converters add a right-half-plane (RHP) zero at D′²R/(DL), which limits achievable bandwidth because increasing duty cycle initially reduces output voltage before the inductance effect kicks in. Flyback converters behave like buck-boost converters in CCM.
Peak current mode uses the exact small-signal response of the switching converter with the inductor-current loop closed, which includes its sampling behaviour near half the switching frequency (Ridley's model approximates it). The sense resistor sets the current-sense gain; the optional external ramp sets slope compensation. Above 50% duty cycle the inductor-current loop needs mc·D′ > 0.5, where mc = 1 + Se/Sn; without it the loop oscillates at Fsw/2 and the tool reports it as subharmonically unstable instead of giving margins.
Valid band: both models describe the converter only below Fsw/2. A loop whose gain is still above 0 dB there crosses over where neither applies, so no margin is reported and the loop is not called stable.
Stability criteria: Phase margin > 45° and gain margin > 10 dB are the standard targets. Insufficient PM causes ringing and slow transient recovery; excessive PM wastes bandwidth. PM < 0° or GM < 0 dB means the closed-loop system is unstable.
Monte Carlo yield predicts what percentage of manufactured units will meet both stability criteria simultaneously, accounting for component value spread across production tolerances. A trial with no margin counts as a failure and is reported separately, not averaged into the margin statistics. This directly answers whether your design is robust enough to manufacture without per-unit calibration.
Related Calculators
Read the Guide
FAQ
What is phase margin and why does > 45° matter?+
Phase margin is the additional phase shift the loop can tolerate before going unstable (where total loop phase reaches -180°). 45° is the classic rule-of-thumb: it gives a step-load overshoot of ~23% and a Q factor of about 0.7 for the closed-loop response. PM < 30° causes excessive ringing; PM > 70° may indicate unnecessarily low bandwidth.
Why does boost/buck-boost have a RHP zero?+
A right-half-plane zero causes the output to initially decrease when duty cycle increases — the opposite of what the control loop expects. This limits the maximum achievable crossover frequency to roughly 1/5 to 1/3 of the RHP zero frequency. Trying to compensate for this with higher bandwidth makes the loop unstable.
How do I tune the Type III compensator?+
A common starting point: place the two zeros fz1 and fz2 near the LC resonant frequency (≈ 1/(2π√(LC))) to add phase boost there. Place fp1 at the ESR zero frequency. Place fp2 at half the switching frequency to attenuate switching noise. Then adjust K to set the desired crossover frequency (typically Fsw/5 to Fsw/10).
What does 87% yield mean in practice?+
If your design shows 87% yield, roughly 13 out of 100 units built from parts drawn randomly from their tolerance bands will fail the stability spec (PM < 45° or GM < 10 dB). For consumer products, target > 99% yield. For industrial designs, > 99.9% is typical. Improving yield requires tightening tolerances, widening margins, or changing the circuit topology.