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PDN Impedance Analyzer & Decoupling Capacitor Optimizer

Choose decoupling capacitors for a PCB power delivery network. Enter the plane pair, the regulator and a flat target impedance, and a genetic algorithm finds the capacitor mix that keeps Z_PDN lowest across the decoupling band, which ends at 0.8 × the board's first cavity mode. Above the band the plane-pair cavity sets the impedance; the plot shows its resonances as one observation port sees them, with every capacitor lumped at that port.

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Inputs

FR4 ≈ 4.5; Rogers 4350B ≈ 3.66; Rogers 3003 ≈ 3.0

FR4 ≈ 0.020; Rogers materials ≈ 0.002–0.004

Where the IC draws current (its power pins). Leave blank for the one-third point of the board width: no cavity mode has a voltage null there, so every mode shows on the plot. The board centre hides every mode with an odd index.

Where the IC draws current, along the board length. Leave blank for the one-third point of the board length (see Port X location).

Side of the square through which the IC current enters the planes (roughly its power-pin field). The plane spreading inductance depends on it. A port over an edge is modelled with its image.

VRM control loop bandwidth — the VRM provides low impedance only below this frequency

Inductance between the regulator and the planes (vias, traces, connector), in series with the VRM.

Flat target impedance. Z_PDN is judged against it across the decoupling band, up to 0.8 × the first cavity mode.

Total decoupling capacitor budget the optimizer may place

How It Works

Power-delivery network impedance determines how cleanly a PCB delivers current to ICs. The usual goal is a flat Ztarget up to the highest frequency in the IC's current — where |ZPDN(f)| exceeds it, switching current causes voltage droops that degrade performance or cause logic errors.

This tool models the impedance the IC sees at one observation port, from three branches in parallel:

  1. The regulator — its DC resistance, turning inductive above the VRM bandwidth, in series with the board inductance between the regulator and the planes.
  2. Decoupling capacitors — each MLCC has a series resonance SRF = 1/(2π√LC) where its impedance is minimal (≈ ESR); above SRF it is inductive. Every capacitor is lumped at the port: where it sits on the board is not modelled.
  3. Plane-pair cavity resonances — the power and ground planes form a 2D rectangular cavity resonating at fmn = (c₀/2√εr)√((m/a)² + (n/b)²). The port sees each mode in proportion to cos²(mπx/a)·cos²(nπy/b), so a port on a mode's voltage null does not see it at all. The port is a square of the size you give, which sets the plane's spreading inductance.

The genetic algorithm sweeps integer capacitor counts across 7 standard MLCC values, first minimising the worst |ZPDN|/Ztarget anywhere in the decoupling band, then, among designs within 0.1 dB of that lowest peak, choosing the one that comes closest to the target where the budget can reach it and to the floor (the lowest |Z| any design within the budget achieves) where it cannot. The decoupling band runs from the start of the sweep up to 0.8 × the board's first cavity mode, or to the end of the sweep if that comes first. Frequencies that no design within the budget can bring below the target are reported with their floor, and still count against the verdict. Above the band the cavity sets |Z|. Capacitors lumped at the port are not designed to suppress cavity modes: that depends on the plane stack-up and on where capacitors sit, which this model does not include.

Leave the port blank and it goes to the one-third point (a/3, b/3). No cavity mode has a voltage null there, so every mode shows on the plot. The board centre, a common choice, hides every mode with an odd index.

Methodology & References

References

  • Frequency-Domain Characterization of Power Distribution Networks — István Novak and Jason R. Miller, Artech House (2007)
  • Power Integrity Modeling and Design for Semiconductors and Systems — Madhavan Swaminathan and A. Ege Engin, Prentice Hall (2007)

Backend reference tests check the plane capacitance and the cavity mode frequencies against their closed forms, and the plane impedance against an independent 2-D plane-pair grid solver.

Related Calculators

Decoupling Capacitor

Read the Guide

PDN Impedance: Cavity Resonance & Decoupling Tips

A practical walkthrough of the PDN Impedance Analyzer: modeling VRM impedance and plane-pair resonances, and choosing capacitors with a genetic algorithm.

FAQ

Why does Z_PDN spike at certain frequencies even with decoupling capacitors?+

There are two kinds of spike. Inside the decoupling band, anti-resonances form where one group of capacitors turns inductive while the next is still capacitive; the optimizer chooses the mix to keep those below the target. Above the band, the spikes are plane-pair cavity resonances: the power and ground planes act as a 2D cavity resonating at frequencies set by the board dimensions and the dielectric constant. The tool lumps every capacitor at one observation port and does not model where capacitors sit, so it does not design them to suppress cavity modes. The resonance list gives each mode's coupling to the port; a mode marked not seen at this port sits on a voltage null there but still exists elsewhere on the board.

What does the convergence history plot show?+

The GA fitness is max(|Z_PDN|/Z_target) on the frequency grid across the whole decoupling band: the ratio of the worst impedance to the target. Among designs whose worst case is within 0.1 dB of the best, the optimiser then prefers the one that keeps the rest of the band lowest, judged against the target where it is reachable and against the floor where it is not. The verdict and the worst case come from the finished design, refined to the true peaks between grid points, so they can read higher than the last fitness value. If the fitness plateaus well above 1.0, relax the target impedance or raise the capacitor budget.